A counter unit constituting a programmable controller connects to an external device, such as an encoder, counts pulses input from the external device, and stores the current count value in an internal memory.
A CPU unit outputs a synchronous control signal with a constant period to the counter unit. Upon receiving the synchronous control signal, the counter unit latches the current count value of the pulses input from the external device, such as an encoder, in the internal memory.
In this way, the timing at which the counter unit latches the current count value in the internal memory is synchronized with the timing at which the CPU unit starts to execute a program. Thus, the current count value with a stable constant period can be obtained.